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july 2008 rev 6 1/28 1 m36w0rx0x0ul4 32- or 64-mbit (mux i/o, multiple bank, multilevel, burst) flash memory, 16- or 32-mbit psram, 1.8 v supply mcp features multichip package ? 1 die of 32 mbit (2 mbit x 16) or 64 mbit (4 mbit x 16) mux i/o multiple bank, multilevel, burst) flash memory ? 1 die of 16/32 mbit mux i/o, burst psram supply voltage ?v dd = v ddq = 1.7 to 1.95 v ?v ppf = 9 v for fast programming electronic signature ? manufacturer code: 20h ? 32 mbit flash device codes: top - m36w0r5040u4: 8828h bottom - m36w0r5040l4: 8829h ? 64 mbit flash device codes: top - m36w0r6040u4 and m36w0r6050u4: 88c0h bottom - m36w0r6040l4 and m36w0r6050l4: 88c1h flash memory synchronous/asynchronous read ? synchronous burst read mode: 66 mhz ? random access: 70 ns synchronous burst read suspend programming time ? 10 s by word typical for factory program ? double/quadruple word program option memory blocks ? multiple bank memory array: 4 mbit banks ? parameter blocks (top or bottom location) dual operations ? program erase in 1 bank, read in others ? no delay between read and write common flash interface (cfi) block locking ? all blocks locked at power-up ? any combination of blocks can be locked ?wp for block lock-down security ? 128 bit user programmable otp cells ? 64 bit unique device number 100 000 program/erase cycles per block psram asynchronous modes ? random read 70 ns access time ? asynchronous write synchronous mode: ? nor flash ? full synchronous (burst read and write) burst read/write operations ? 4-, 8- and 16-word ? clock frequency: 83 mhz low power consumption ? active current: < 20 ma ? standby current: 70 a low power features ? partial array self-refresh (pasr) ? deep power-down (dpd) mode ? automatic temperature-compensated self- refresh (atsr) table 1. device summary m36w0rx0x0ul4 m36w0r5040u4 m36w0r5040l4 m36w0r6040u4 m36w0r6040l4 m36w0r6050u4 m36w0r6050l4 tfbga56 (zs) 8 x 6 mm tfbga88 (zam) 8 x 10 mm www.numonyx.com
contents m36w0rx0x0ul4 2/28 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 common signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1 data inputs/outputs (adq0-adq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.2 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.3 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.4 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.5 flash memory chip enable (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.6 flash memory write protect (wp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.7 flash memory reset (rp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.8 psram chip enable (e p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.9 psram upper byte enable (ub p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.10 psram lower byte enable (lb p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.11 psram configuration register enable (cr p ) . . . . . . . . . . . . . . . . . . . . 12 2.1.12 v ppf flash memory program supply voltage . . . . . . . . . . . . . . . . . . . . . 13 2.1.13 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.14 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 tfbga56 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 tfbga56 address inputs (adq0-adq15 and a16-a21) . . . . . . . . . . . 13 2.2.2 deep power-down (dpd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.4 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.5 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.6 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 tfbga88 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 tfbga88 address inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.2 flash memory output enable (g f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 flash memory write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.4 v ddf flash memory supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 v ccp psram supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 psram output enable (g p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 psram write enable (w p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
m36w0rx0x0ul4 contents 3/28 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
list of tables m36w0rx0x0ul4 4/28 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. tfbga56 package operating modes - standard asynchronous operation . . . . . . . . . . . . . 18 table 4. tfbga88 package operating modes - standard asynchronous operation . . . . . . . . . . . . . 19 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. tfbga56 8 6 x 1.2 mm, 10 x 6 ball array - 0.5 mm pitch, package data . . . . . . . . . . . . 24 table 9. stacked tfbga88 8 10 mm - 8 10 active ball array, 0.8 mm pitch, package data . . . 25 table 10. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
m36w0rx0x0ul4 list of figures 5/28 list of figures figure 1. logic diagram - tfbga56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram - tfbga88 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tfbga56 package connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. tfbga88 package connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. functional block diagram - tfbga56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. functional block diagram - tfbga88 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 8. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. tfbga56 8 6 x 1.2 mm, 10 x 6 ball array - 0.5 mm pitch, bottom view package outline 23 figure 10. tfbga88 8 10 mm, 8 10 ball array - 0.8 mm pitch, bottom view package outline. . . . 24
description m36w0rx0x0ul4 6/28 1 description the m36w0r5040u4, m36w0r5040l4, m36w0r6040u4, m36w0r6040l4, m36w0r6050u4, and m36w0r6050l4 each combine two memory devices in a multichip package: a 32-mbit or 64-mbit, multiple bank flash memory, the m58wr0xxkul either: ? a 16-mbit pseudo sram, the m69km024a ? a 32-mbit pseudo sram, the m69km048a. collectively, these four devices are referred to in this document as the m36w0rx0x0ul4. the purpose of this document is to describe how the two memory components operate with respect to each other. it must be read in conjunction with the m58wr0xxkul, and m69km024a or m69km048a datasheets, which detail all the specifications required to operate the flash memory and psram components. these datasheets are available from your local numonyx distributor. the memory is offered in two stacked packages: tfbga56 (8 x 6 mm, 10 x 6 ball array, 0.5 mm pitch) package tfbga88 (8 x 10 mm, 8 x 10 ball array, 0.8 mm pitch) package recommended operating conditions do not allow more than one memory to be active at the same time. figure 1. logic diagram - tfbga56 package ai14405f 6 a16-a21 adq0-adq15 m36w0rx0x0ul4 g 16 w rp f wp f ub p lb p v ss v dd v ppf wait l k v ddq e f cr p v ssq e p dpd
m36w0rx0x0ul4 description 7/28 figure 2. logic diagram - tfbga88 package ai13541d 6 a16-a21 adq0-adq15 m36w0rx0x0ul4 g f 16 w f rp f wp f e p g p w p ub p lb p v ss v ddf v ppf v ddp wait l k v ddqf e f cr p
description m36w0rx0x0ul4 8/28 table 2. signal names name function direction common to both packages a16-a21 (1) 1. in the tfbga56 package, address inputs a16-a18 in the psram are used in conjunction with adq0 to adq15 to select the cells in the memory arra y that are accessed duri ng read and write operations. however, in the tfbga88 package, it is is address inputs a16-a19. address inputs inputs adq0-adq15 flash memory and psram common data input/outputs, address inputs or command inputs inputs/outputs l flash memory and psram latch enable input input k flash memory and psram burst clock input wait flash memory and psram wait data in burst mode output e f flash memory chip enable input input wp f flash memory write protect input input rp f flash memory reset input input e p psram chip enable input input ub p psram upper byte enable input input lb p psram lower byte enable input input cr p psram configuration register enable input input v ppf flash memory optional supply voltage for fast program and erase power supply v ss flash memory and psram shared ground ground v ssq flash memory and psram shared ground. ground nc not connected internally only in tfbga56 package dpd deep power-down input g flash memory and psram output enable input input w flash memory and psram write enable input input v dd flash memory and psram shared power supply power supply v ddq flash memory and psram shared power supply for i/o buffers power supply only in tfbga88 package g f flash memory output enable input input w f flash memory write enable input input g p psram output enable input input w p psram write enable input input v ddf flash memory power supply power supply v ccp psram supply voltage is the core supply voltage. power supply
m36w0rx0x0ul4 description 9/28 figure 3. tfbga56 package connections (top view through package) 3 2 nc ad15 nc a16 ad6 a20 v ssq v ss ad13 ad5 ad4 ad12 nc cr p ad11 ad3 ad10 ad2 v ddq ad9 ad1 ad8 nc 1 ai14406d ad7 ad14 a18 v ss wait v ddq nc ad0 v ssq 4 5 6 7 8 9 10 11 12 13 14 a c nc nc lb p ub p nc nc a21 k v dd w v ppf a19 a17 nc l e f g e p d e f g h b i j wp f rp f
description m36w0rx0x0ul4 10/28 figure 4. tfbga88 package connections (top view through package) 8 7 6 5 4 3 2 1 c b a21 k nc nc d e f du du w f v ss a19 a18 nc nc nc v ss nc lb p nc nc nc v ppf nc a17 nc a20 nc nc l wp f nc nc nc nc nc a16 rp f ub p nc wait adq13 nc adq5 adq10 adq2 adq8 adq7 adq14 g p adq12 adq3 adq1 adq0 adq15 adq6 adq4 adq11 adq9 g f v ddqf e f cr p v ddp v ss v ss v ss v ss v ss v ddf v ddqf v ss du du du du du du a g h j k ai12838b l m v ddf nc w p e p nc nc du du nc nc nc nc v ddqf
m36w0rx0x0ul4 signal descriptions 11/28 2 signal descriptions see figure 1: logic diagram - tfbga56 package and table 2: signal names for a brief overview of the signals connected to this device. there are some signals that are not common to both device packages and are, therefore, explained separately. 2.1 common signals the following are the signals that are the same for the tfbga56 package and the tfbga88 package. 2.1.1 data inputs/outputs (adq0-adq15) the data i/o output the data stored at the selected address during a bus read operation, or they input a command or the data to be programmed during a bus write operation. 2.1.2 latch enable (l ) the latch enable input is common to the flash memory and psram components. for more details on the latch enable signal, please refer to the datasheets of the respective memory components: m69km024a or m69km048a for the psram and m58wr0xxkul for the flash memory. 2.1.3 clock (k) the clock input is common to the flash memory and psram components. for more details on the clock signal, please refer to the datasheets of the respective memory components: m69km024a or m69km048a for the psram and m58wr0xxkul for the flash memory. 2.1.4 wait (wait) the wait output is common to the flash memory and psram components. for details on the wait signal, please refer to the datasheets of the respective memory components:m69km024a or m69km048a for the psram and m58wr0xxkul for the flash memory. 2.1.5 flash memory chip enable (e f ) the flash memory chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when flash memory chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. it is not allowed to set both e f and e p to v il at the same time.
signal descriptions m36w0rx0x0ul4 12/28 2.1.6 flash memory write protect (wp f ) write protect is an input that provides additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or unlocked (refer to the m58wr0xxkul datasheet). 2.1.7 flash memory reset (rp f ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to the m58wr0xxkul datasheet for the value of i dd2. after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. when the device exits reset mode it enters asynchronous read mode. however, a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3 v logic without any additional circuitry, and can be tie to v rph (refer to the m58wr0xxkul datasheet). 2.1.8 psram chip enable (e p ) chip enable, e p , activates the psram device when driven low (asserted). when de- asserted (v ih ), the device is disabled and goes automatically into low-power standby mode or deep power-down mode, according to the rcr settings. it is not allowed to set both e f and e p to v il at the same time. 2.1.9 psram upper byte enable (ub p ) the upper byte enable, ub p , gates the data on the upper byte of the address inputs/data inputs/outputs (adq8-adq15) to or from the upper part of the selected address during a write or read operation. 2.1.10 psram lower byte enable (lb p ) the lower byte enable, lb p , gates the data on the lower byte of the address inputs/data input/outputs (adq0-adq7) to or from the lower part of the selected address during a write or read operation. if both lb p and ub p are disabled (high), the device prevents the data bus from receiving or transmitting data. although the device seems to be deselected, it remains in an active mode as long as e p remains low. 2.1.11 psram conf iguration register enable (cr p ) when this signal is driven high, v ih , bus read or write operations access either the value of the refresh configuration register (rcr) or the bus configuration register (bcr), according to the value of a19.
m36w0rx0x0ul4 signal descriptions 13/28 2.1.12 v ppf flash memory program supply voltage v ppf is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0 v to v ddq ), v ppf acts as a control input. in this case a voltage lower than v pplk gives absolute protection against program or erase, while v ppf in the v pp1 range enables these functions (see the m58wr0xxkul datasheet for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pph it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed. 2.1.13 v ss ground v ss ground is the common flash memory and psram ground. it is the reference for the core supplies and must be connected to the system ground. 2.1.14 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddqf . v ssq must be connected to v ss note: each device in a system should have v ddf , v ddqf and v pp decoupled with a 0.1f ceramic capacitor close to the pin (high fre quency, inherently low inductance capacitors should be as close as possible to the package). see figure 8: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents. 2.2 tfbga56 signals 2.2.1 tfbga56 address input s (adq0-adq15 and a16-a21) the following address inputs are common to the flash memory and psram components: adq0-adq15, and a16- a19 when stacked with a 16-mbit psram, or a16-a20 when stacked with a 32-mbit psram. in the flash memory, the address inputs select the cells in the array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. in the psram, the address following inputs ar e used in conjunction with adq0 to adq15 to select the cells in the memory array that are accessed during read and write operations: a16- a19 when stacked with a 16-mbit psram, or a16-a20 when stacked with a 32-mbit psram. a21 is an address input for the 64-mbit flash memory device only.
signal descriptions m36w0rx0x0ul4 14/28 2.2.2 deep power-down (dpd) the deep power-down input puts the device in deep power-down mode. when the device is in standby mode and the enhanced configuration register bit ecr15 is set, asserting the deep power-down input causes the memory to enter deep power-down mode. when the device is in deep power-down mode, the memory cannot be modified and the data is protected. the polarity of the dpd pin is determined by ecr14. the deep power-down input is active low by default. 2.2.3 output enable (g ) the output enable input is common to the flash memory and psram components. for details on the output enable signal, please refer to the datasheets of the respective memory components: m69km024a or m69km048a for the psram and m58wr0xxkul for the flash memory. 2.2.4 write enable (w ) the write enable input is common to the flash memory and psram components. for details on the write enable signal, please refer to the datasheets of the respective memory components: m69km024a or m69km048a for the psram and m58wr0xxkul for the flash memory. 2.2.5 v dd supply voltage v dd is common to both flash memory and psram components and provides the power supply to the internal core. it is the main power supply for all memory operations (read, program, and erase). 2.2.6 v ddq supply voltage v ddq is common to both flash memory and psram components and provides the power supply to the i/o pins. it enables all outputs to be powered independently of v dd . v ddq can be tied to v dd or use a separate supply. 2.3 tfbga88 signals 2.3.1 tfbga88 address inputs the following address inputs are common to the flash memory and psram components: adq0-adq15, and a16- a19 when stacked with a 16-mbit psram, or a16-a20 when stacked with a 32-mbit psram. a21 is an address input for the 64-mbit flash memory component only.
m36w0rx0x0ul4 signal descriptions 15/28 in the psram, the address following inputs ar e used in conjunction with adq0 to adq15 to select the cells in the memory array that are accessed during read and write operations: a16- a19 when stacked with a 16-mbit psram, or a16-a20 when stacked with a 32-mbit psram. in the flash memory, the address inputs select the cells in the array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.3.2 flash memory output enable (g f ) the output enable input controls data outputs during the bus read operation of the flash memory. 2.3.3 flash memory write enable (w f ) the write enable input controls the bus write operation of the flash memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable, whichever occurs first. 2.3.4 v ddf flash memory supply voltage v ddf provides the power supply to the internal core of the flash memory. it is the main power supply for all flash memory operations (read, program, and erase). 2.3.5 v ccp psram supply voltage the v ccp supply voltage is the core supply voltage. 2.3.6 psram output enable (g p ) when held low, v il , the output enable, g p , enables the bus read operations of the memory. 2.3.7 psram write enable (w p ) write enable, w p , controls the bus write operation of the memory. when asserted (v il ), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array.
functional description m36w0rx0x0ul4 16/28 3 functional description the psram and flash memory components share the same power supplies and the same grounds. they are distinguished by two chip enable inputs: e f for the flash memory and e p for the psram. recommended operating conditions do not allow more than one device to be active at a time, such as simultaneous read operations on the flash memory and the psram component, which would result in a data bus contention. therefore, it is recommended to put the other device in the high impedance state when reading the selected device. figure 5 outlines the functional block diagram for the tfbga56 package, while figure 6 outlines the one for tfbga88 package. figure 5. functional block diagram - tfbga56 package 1. a20 for the m36w0r5040x4, a20-a21 for the m36w0r6040x4, and a21 for the m36w0r6050x4. 2. amax is equal to a19 when stack ed with a 16-mbit psram, or a20 when stacked with a 32-mbit psram. ai14407f e p cr p g w adq0-adq15 v ppf a16-amax (2) a20 or a20-a21 or a21 (1) 16 or 32 mbit psram ub p lb p wait k v ss 32 or 64 mbit flash memory v dd l rp f wp f e f v ddq v ssq dpd
m36w0rx0x0ul4 functional description 17/28 figure 6. functional block diagram - tfbga88 package 1. a20 for the m36w0r5040x4, a20-a21 for the m36w0r6040x4, and a21 for the m36w0r6050x4. 2. amax is equal to a19 when stack ed with a 16-mbit psram, or a20 when stacked with a 32-mbit psram. ai12339c e p cr p g p w p adq0-adq15 v ppf a16-amax (2) a20 or a20-a21 or a21 (1) 16 or 32 mbit psram g f ub p lb p wait k v ddqf v ss 32 or 64 mbit flash memory v ddf v ccp l rp f wp f w f e f
functional description m36w0rx0x0ul4 18/28 table 3. tfbga56 package operating modes - standard asynchronous operation operation (1)(2) 1. the clock signal, k, must remain low when the psram is operating in asynchronous mode. 2. x = ?don?t care? e f rp f wait (3) 3. in the flash memory the wait signal polarity is co nfigured using the set conf iguration register command. g w l ub p lb p cr p e p adq0- adq7 adq8 -adq15 flash memory bus read v il v ih v il v ih v ih any psram mode is allowed. data output bus write v il v ih v ih v il v ih data input address latch v il v ih v ih xv il data output or hi-z (4) 4. see the m58wr0xxkul datasheet. output disable v il v ih v ih v ih v ih any psram mode is allowed. hi-z standby v ih v ih hi-z x x x hi-z reset x v il hi-z x x x hi-z psram word read the flash memory must be disabled. v il v ih \_/ v il v il v il v il address in/ data out valid word write v ih v il v il v il v il address in/ data in valid output disable/no operation any flash memory mode is allowed. v ih v ih xx x v il high-z deep power- down (5) 5. the device enters deep power-down mode by driving the chip enable signal, e , from low to high, with bit 4 of the rcr set to ?0?. the device remains in deep power-down mode until e goes low again and is held low for t eleh(dp) . xxxx x x v ih high-z standby x x x x x x v ih high-z
m36w0rx0x0ul4 functional description 19/28 table 4. tfbga88 package operating modes - standard asynchronous operation (1) operation (2) e f g f w f rp f wait (3) l p e p w p g p ub p lb p cr p a19 a16- a18 adq0- adq7 adq8- adq15 flash memory bus read v il v il v ih v ih v ih the psram must be disabled data output bus write v il v ih v il v ih v ih data input address latch v il v ih xv ih v il address input output disable v il v ih v ih v ih v ih any psram mode is allowed hi-z standby v ih xxv ih hi-z x hi-z reset xxxv il hi-z x hi-z psram word read \_/ v il v ih v il v il v il v il address in valid address in/data out valid word write v il v ih v il v il v il address in valid address in/ data in valid output disable/no operation x v ih xxxv il x high-z deep power- down (4) v ih x x x x x x high-z standby v ih xxx x xv il x high-z 1. x = ?don?t care? 2. the clock signal, k, must remain low in asynchronous operating mode. 3. in the flash memory the wait si gnal polarity is configur ed using the set configuration register command. 4. the device enters deep power-down mode by driving the ch ip enable signal, e , from low to high, with bit 4 of the rcr set to ?0?. the device remains in deep power-down mode until e goes low again and is held low for t eleh(dp) .
maximum ratings m36w0rx0x0ul4 20/28 4 maximum ratings stressing the device above the ratings listed in table 5: absolute maximum ratings may cause permanent damage to the device. these are only stress ratings and operating the device at these or any other conditions above those indicated in the operating sections of this specification is not suggested. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 5. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?30 85 c t bias temperature under bias ?30 85 c t stg storage temperature ?55 125 c v io input or output voltage ?0.2 2.45 v v dd , v ddq flash and psram core and input/output supply voltages ?0.2 2.45 v v ppf flash program voltage ?0.2 10 v i o output short circuit current 100 ma t vppfh time for v ppf at v ppfh 100 hours
m36w0rx0x0ul4 dc and ac parameters 21/28 5 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 6: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 7. ac measurement i/o waveform table 6. operating and ac measurement conditions parameter flash memory psram unit min max min max v dd supply voltage 1.7 1.95 ? ? v v ddq supply voltage 1.7 1.95 ? ? v v ppf supply voltage (factory environment) 8.5 9.5 ? ? v v ppf supply voltage (application environment) ?0.4 v ddq +0.4 ? ? v ambient operating temperature ?30 85 ?30 85 c load capacitance (c l )3030pf output circuit resistors (r 1 , r 2 ) 16.7 16.7 k input rise and fall times 5 2 ns input pulse voltages 0 to v ddq 0 to v dd /2 v input and output timing ref. voltages v ddq /2 v dd /2 v ai06161 v ddq 0 v v ddq /2
dc and ac parameters m36w0rx0x0ul4 22/28 figure 8. ac measurement load circuit please refer to the m58wr0xxkul and the m69km024a or m69km048a datasheets for further dc and ac characteristics values and illustrations. table 7. device capacitance symbol parameter test condition min max (1) 1. sampled only, not 100% tested. unit c in input capacitance v in = 0 v 14 pf c out output capacitance v out = 0 v 18 pf ai08364e v ddq c l c l includes jig capacitance r 1 device under test 0.1 f v ddq r 2 0.1 f v dd
m36w0rx0x0ul4 package mechanical 23/28 6 package mechanical to meet environmental requirements numonyx offers these devices in ecopack? packages, which have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack specifications are available at: www.numonyx.com . figure 9. tfbga56 8 6 x 1.2 mm, 10 x 6 ball array - 0.5 mm pitch, bottom view package outline 1. drawing is not to scale. jv_me ddd d e e b a2 a a1 e2 se fd1 fe e1 e d1 sd d2 ball "a1" fd fe1
package mechanical m36w0rx0x0ul4 24/28 figure 10. tfbga88 8 10 mm, 8 10 ball array - 0.8 mm pitch, bottom view package outline 1. drawing is not to scale. table 8. tfbga56 8 6 x 1.2 mm, 10 x 6 ball array - 0.5 mm pitch, package data symbol millimeters inches typ min max typ min max a1.200.047 a1 0.15 0.0006 a2 0.79 0.031 b 0.30 0.25 0.35 0.012 0.010 0.014 d 6.00 5.90 6.10 0.236 0.232 0.240 d1 4.50 0.177 e 4.00 3.90 4.10 0.157 0.154 0.161 e1 2.50 0.098 e0.50 0.020 fd 0.75 0.030 fe 0.75 0.030 sd 0.25 0.010 a2 a1 a bga-z42 ddd d e e b se fd e2 d1 sd ball "a1" e1 fe fe1
m36w0rx0x0ul4 package mechanical 25/28 table 9. stacked tfbga88 8 10 mm - 8 10 active ball array, 0.8 mm pitch, package data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 0.2205 ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 0.2835 e2 8.800 0.3465 e 0.800 ? ? 0.0315 ? ? fd 1.200 0.0472 fe 1.400 0.0551 fe1 0.600 0.0236 sd 0.400 0.0157 se 0.400 0.0157
part numbering m36w0rx0x0ul4 26/28 7 part numbering note: devices are shipped from the factory with the memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest numonyx sales office. table 10. ordering information scheme example: m36 w 0 r 5 0 4 0 u 4 zs f device type m36 = multichip package (flash + ram) flash 1 architecture w = multiple bank, burst mode flash 2 architecture 0 = no die operating voltage r = v dd = v ddq = 1.7 v to 1.95 v flash 1 density 5 = 32 mbit 6 = 64 mbit flash 2 density 0 = no die ram 1 density 4 = 16 mbit 5 = 32 mbit ram 2 density 0 = no die parameter block location u = top block flash l = bottom block flash product version 4 = 65 nm flash technology and multilevel design, 70 ns speed class; ram, 70 ns speed mux i/o package zs = stacked tfbga56 8 x 6 mm - 10 x 6 active ball array, 0.50 mm pitch zam = stacked tfbga88 8 10 mm - 8 10 active ball array, 0.8 mm pitch packing option e = ecopack? package, standard packing f = ecopack? package, tape and reel packing
m36w0rx0x0ul4 revision history 27/28 8 revision history table 11. document revision history date revision changes 24-oct-2007 1 initial release. 30-oct-2007 2 modified the device codes on page 1. 26-mar-2008 3 added the m36w0r5040u4 and m36w0r5040l4 root part numbers and all their associated data throughout this document. applied numonxy branding. 29-apr-2008 4 replaced the m69km048ab with m69km048a everywhere in the document. corrected the product version in table 10: ordering information scheme . 20-may-2008 5 changed the maximum flash frequency from 86 mhz to 66 mhz on page 1. 17-jul-2008 6 changed the ambient operating temperature from -25 to -30 in table 5: absolute maximum ratings and table 6: operating and ac measurement conditions .
m36w0rx0x0ul4 28/28 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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